The present invention is suitably applied to impedance adjustment of an output buffer of a DDR (Double Data Rate) 2 memory having an OCD (Off-Chip Driver) impedance adjusting function in a memory interface. A background art of the present invention will be described below.
As a conventional approach to OCD impedance adjustment, the impedance adjustment of an output buffer of a memory controller connected to the DDR2 memory will be described below. In the case of the output buffer of the memory controller, there is no influence of a series resistance on a package (PKG)/system board/DIMM (Dual Inline Memory Module) and hence the impedance adjustment can be performed with relative ease. A method of adjusting an impedance of an output buffer in a memory controller 10 shown in FIG. 11 will be described. FIG. 12A through FIG. 12C are diagrams for explaining the impedance adjustment of the output buffer A in FIG. 11.
As shown in FIG. 12A, in an impedance circuit, a resistance R11 is inserted between a power supply VCC and a node 101, which is an output node of the output buffer A, through a switch SW11. A value obtained by adding a resistance value of the switch SW11 to a resistance value of the resistance R11 becomes a value of a pull-down buffer N11 constituted from an Nch MOS transistor after the impedance adjustment. Likewise, a resistance R12 is inserted between the node 101 and a GND through a switch SW12. A value obtained by adding a resistance value of the switch SW12 to a resistance value of the resistance R12 becomes a value of a pull-up buffer P11 constituted from a Pch MOS transistor after the impedance adjustment. Further, a voltage at the node 101 is supplied to an impedance control circuit 102 together with a reference voltage VREF, for comparison. According to a result of the comparison, a control signal S21 for increasing or reducing buffer size of the pull-up buffer or the pull-down buffer is input to the output buffer A, thereby performing feedback control.
As shown in FIG. 12B, at the time of the impedance adjustment of the pull-up buffer P11, the Nch MOS transistor N11 and the switch SW11 are turned off, and the Pch MOS transistor P11 and the switch SW12 are turned on.
When the voltage at the node 101 is higher than the reference voltage (reference voltage) VREF, the adjustment is made so that the buffer size of the pull-up buffer P11 is reduced in order to increase the impedance of the pull-up buffer 11. When the voltage at the node 101 is lower than the reference voltage (reference voltage) VREF, the adjustment is made so that the buffer size of the pull-up buffer P11 is increased in order to reduce the impedance of the full-up buffer P11.
On the other hand, at a time of the impedance adjustment of the pull-down buffer N11 as shown in FIG. 12C, the pull-up buffer P11 and the switch SW12 are turned off, and the pull-down buffer N11 and the switch SW11 are turned on. When the voltage at the node 101 is higher than the reference voltage VREF, the adjustment is made so that the buffer size of the pull-down buffer N11 is increased in order to reduce the impedance of the pull-down buffer N11.
When the voltage at the node 101 is lower than the reference voltage VREF, the adjustment is made so that the buffer size of the pull-down buffer N11 is reduced in order to increase the impedance of the pull-down buffer N11.
By repeating these series of operations until the voltage at the node 101 becomes the same as the reference VREF, the impedance adjustment of the pull-up buffer P11 or the impedance adjustment of the pull-down buffer NI1 is performed.
The pull-up buffer P11 has a configuration in which a plurality of arbitrary sized Pch MOS transistors are connected in parallel so that the buffer size thereof can be increased or decreased. The pull-down buffer N11 has a configuration in which a plurality of arbitrary sized Nch MOS transistors are connected in parallel so that the buffer size thereof can be increased or decreased. The number of transistors to be connected is controlled by the control signal S21. A channel resistance of each Pch MOS transistor constituting the pull-up buffer P11 is proportional to the reciprocal of the W/L (where W indicates a channel width, and L indicates a channel length). When the channel width W is set to be large (accordingly, when the buffer size is set to be large, by increasing the number of connection of the Pch MOS transistors constituting the pull-up buffer P11 in parallel, for example), the impedance of the pull-up buffer P11 is reduced. When the channel width W is set to be small (when the buffer size is set to be small, by reducing the number of the Nch MOS transistors constituting the pull-up buffer P11 in parallel, for example), the impedance of the pull-up buffer P11 is increased. A channel resistance of each Nch MOS transistor constituting the pull-down buffer N11 is proportional to the reciprocal of the W/L (where W indicates the channel width, and L indicates the channel length). When the channel width W is set to be large (when the buffer size is set to be large, by increasing the number of connection of the Nch MOS transistors constituting the pull-down buffer N11 in parallel, for example), the impedance of the pull-down buffer N11 is reduced. When the channel width W is set to be small (when the buffer size is set to be small, by reducing the number of the Nch MOS transistors constituting the pull-down buffer N11 in parallel, for example), the impedance of the pull-down buffer NI1 is increased.
The DDR2 memory has a function of adjusting the impedance of the output buffer of the DDR2 memory (referred to as an “OCD impedance adjusting function”) by entering into an OCD impedance adjusting mode by an input of a command from an outside. Each OCD mode is set in an extended mode register (1) (EMRS (1)) in a DDR2 SDRAM (Synchronous DRAM), using predetermined bits (such as A7, A8, and A9) of an address signal. In a drive (1) mode, output levels of output signals (DQ, DQS, and DQSB) become preset states. An external device such as the memory controller measures voltage levels of the output signals (DQ, DQS, and DQSB) (more specifically, High levels of the signals DQ and DQS and Low level of the signal DQSB), to check whether a pull-up resistance value has become a target value. In a drive (0) mode, the output levels of the output signals (DQ, DQS, and DQSB) become preset states. The external device such as the memory controller measures the voltage levels of the output signals (DQ, DQS, and DQSB) (more specifically, Low levels of the signals DQ and DQS and High level of the signal DQSB), to check whether a pull-down resistance value has become a target value. An adjustment mode is the mode for adjusting the impedance of the output buffer (output driver). The impedance of the output buffer can be adjusted in 16 stages, for example, and the adjustment is made so that the pull-up resistance and the pull-down resistance of the output signals (DQ, DQS, DQSB) become equal. OCD calibration mode cancellation stops an OCD calibration mode. Setting to an OCD calibration default (in which the impedance of the output driver is set to a default value) is performed. Impedance measurement and comparison are performed by the external device such as the memory controller rather then by the SDRAM. When the drive (1) mode is set, when the pull-up resistance is measured, and when the adjustment needs to be made, the OCD calibration mode cancellation is performed. Then, the adjusting mode is set, the pull-up resistance value (the impedance of the driver) is adjusted, and the OCD calibration mode cancellation is performed. The pull-down resistance is also measured and adjusted (refer to Non-Patent Document 1) similarly.
When the impedance adjustment of the output buffer on the side of DDR2 memory (DIMM) is made, an impedance control circuit needs to be inserted into the memory controller.
However, between the memory controller and the DDR2 memory, series resistance components including a parasitic resistance on each of a package (PKG), a system board, and a DIMM (Dual Inline Memory Module) are present.
Since these series resistance components differ in dependence on a chip set and a memory vendor, identification of the components in a design phase is difficult.
Accordingly, an offset portion of the impedance of the output buffer caused by the series resistance components cannot be eliminated. Thus, under present circumstances, there is no effective impedance adjusting method.
When the impedance of the pull-up output buffer on the side of the DDR2 memory (DIMM) and the impedance of the pull-down output buffer on the DDR2 memory (DIMM) side are different, slew rates of a rise/fall of output signals of the pull-up output buffer and the pull-down output buffer become different.
As an influence caused by this, a voltage at a cross-point between differential strobe signals (DQS, DQSB) for data control, which are specific to the DDR2 memory, may be deviated from a reference voltage VREF (0.5*VCC).
In order to reduce an influence of power supply noise, the output signals from the DDR2 memory are generally amplified (differential amplified) by a differential amplifier that uses the reference voltage VREF in the memory controller. However, when the voltage at the crosspoint between the signals DQS and DQSB is deviated from the reference voltage VREF as described before, this deviation is seen as a jitter in the memory controller, thereby adversely affecting characteristics of the DDR2 memory.
Then, since the DDR2 memory targets a high-speed operation at the frequency of 400 Mbps (with one clock cycle tCK being 5 n sec) or higher, suppression of a jitter component in the DDR2 memory has become an extremely important challenge.    [Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-11-177380    [Non-patent Document 1]
Technical Note, New Functions of DDR2 SDRAM, Off-Chip Driver (OCD), January 2005, Document No. J0594E10 (Ver. 1.0) <Internet: URL “http://www.elpida.com”>